(a) Field of the Invention
The present invention relates to a panel assembly for a display device, a display device including the same, and a repairing method of the display device.
(b) Description of the Related Art
The demand is increasing for flat panel displays, such as plasma panel assemblys (“PDPs”), organic light emitting displays (“OLEDs”), and liquid crystal displays (“LCDs”).
PDPs are devices that display characters or images using plasma generated by gas-discharge. OLEDs are devices which display characters or images by applying an electric field to specific light-emitting organic or high molecule materials. LCDs are devices which display images by applying an electric field to a liquid crystal layer disposed between two panels, and regulating the strength of the electric field to adjust a transmittance of light passing through the liquid crystal layer.
The flat panel displays, for example, the LCD and the OLED, each include a panel unit provided with pixels including switching elements and display signal lines, and a gate driving IC for transmitting gate signals to gate lines among the display signal lines to turn on/off the switching elements of the pixels, a gray voltage generator for generating a plurality of gray voltages, a data driving IC for applying data voltages to data lines among the display signal lines, and a signal controller for controlling the components.
The signal controller and the gray voltage generator are disposed on a printed circuit board PCB which is located outside of the panel assembly. The driving IC is mounted on a flexible printed circuit film FPC which is located between the PCB and the panel assembly. Generally, two PCBs are provided. In this case, the two PCBs are disposed at upper and left sides of the panel assembly, and the upper and left side PCBs are referred as gate and data PCBs, respectively. The gate driving IC is disposed between the gate PCB and the panel assembly, and the data driving IC is disposed between the data PCB and the panel assembly. The gate and data driving ICs receive signals from the gate and data PCBs, respectively.
However, without the use of the gate and data PCBs, the gate and data driving ICs may be disposed just on an upper side of the panel assembly as a chip on glass (COG) type.
On the other hand, in order to detect defects such as disconnections and short-circuits during the production of the display device, various test processes are performed. For example, an array test, a visual inspection (VI) test, a gross test, and a module test are performed.
The array test is a test for detecting occurrence of disconnection of the display signal lines by applying a predetermined voltage and detecting the presence or absence of an output signal before a mother glass is divided into individual cells. The VI test is a test for visually detecting occurrence of disconnections of the display signal lines by assembling the upper panel with the lower panel and applying a predetermined voltage, after the mother glass is divided into the individual cells. The gross test is a test for detecting an image quality and occurrence of disconnections of the display signal lines by applying a voltage equal to an actual driving voltage and checking a display state on a screen before the driving circuit is mounted. The module test is a test for finally checking whether or not the driving circuit properly operates after the driving circuit is mounted.
In these tests, end portions of the gate lines and the data lines are formed as pads having wide ends in order to improve a contacting property to an external device.
Particularly, in order to perform the test under the same conditions as when driving the ICs, in the gross test, a gross test unit reproduces the same conditions as when driving ICs is used, and a test signal is applied by contacting probes such as needles connected to the gross test unit with the pads.
For example, when the data driving ICs are mounted on an FPC, the gross test unit mounts a test data driving IC on the FPC (a TCP (tape carrier package) scheme). Connection portions where wire lines are formed are disposed between the FPC and the probes, and signals are applied to the data lines through the probes disposed at end portions of the connection portions.
In addition, if the data driving ICs are mounted in a COG scheme, the test data driving IC is mounted on a glass substrate, and signals are applied to the data lines through the probes.
Here, the gross test includes two test steps. As described above, one step is a test of occurrence of disconnection of the display signal lines after a predetermined signal is applied through the gross test unit, and the other step is a test of success in repairing the disconnected signal lines.
In a case where the driving ICs are mounted in a COG scheme, the gross test unit must be a COG type of test unit that is suitable for the COG scheme.
However, unlike the TCP type test unit where the connection portions are separately provided, in the COG type test unit, the connected portions are provided in an integral form, and the COG type of test units matching with a resolution of the associated display device must be used. Therefore, since separate test units matching with the display devices having different resolutions must be manufactured, production costs increase.
In order to solve the problem in the production costs, a TCP type of test unit may be used to test the COG type of data driving IC. However, in a case of the TCP type of data driving IC, two auxiliary repair lines are connected at one side of the data driving IC, and in case of the COG type of data driving IC, two auxiliary repair lines are connected at both sides of the data driving IC, respectively. Therefore, due to the structural difference, there is a problem in that it is difficult to detect the repaired state after the disconnected signal lines are repaired.